1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device provided with a test mode in addition to a normal mode.
2. Description of the Related Art
Among semiconductor devices including semiconductor memories, ones provided with test modes for executing operation tests have been known. A semiconductor device is changed from a normal mode to a test mode by applying a test mode setting signal to a test pad on the chip. In order to change from a normal mode to a test mode easily in a short time, the states of being assembled in packages have been ideal for executing operation tests of semiconductor devices. Recently, in order to reduce the number of input terminals, one having a common terminal used as both a normal signal input terminal and a test input terminal is being developed.
In general, a semiconductor device comprising an input terminal, an input circuit connected to the input terminal, and a high-voltage detector connected to the input terminal and the input circuit has been known. A CMOS inverter is provided on the input side of the input circuit. The CMOS inverter comprises pMOS and nMOS transistors. The gate terminals of the pMOS and nMOS transistors are respectively connected to the input terminal. The drain terminals of the pMOS and nMOS transistors form the output terminal of the CMOS inverter. The source terminal of the pMOS transistor is connected to the power supply side. The source terminal of the nMOS transistor is connected to the ground side.
When a voltage for a normal mode is inputted, the input circuit outputs a normal mode signal. When the voltage inputted from the input terminal reaches a threshold value or more, the high-voltage detector outputs a test mode signal. Specifically, the semiconductor device switches between the normal mode and the test mode in accordance with the voltage of a signal inputted from the input terminal.
However, in semiconductor devices including semiconductor memories, process parameters including the threshold voltages of transistors used in high-voltage detectors have varied. Therefore, detected voltages have had errors. In the worst case, a system using a memory may be changed from a normal mode to a test mode due to a malfunction caused by noise. In order to prevent malfunctions, there is a method of setting a test mode setting voltage higher. If a test mode setting voltage is raised, a higher voltage is constantly applied to the input side of an input circuit. On the other hand, the scaling of vertical structures has been progressed by miniaturization, and gate oxide films have been thinned. Since gate oxide films have become thinner, the application of high voltages to the input sides of input circuits has been concerned that the application causes reliability problems. There has been a problem that, if gate oxide films became yet thinner in the future, the application of high voltages to the input sides of input circuits would become increasingly unpreferable in terms of reliability.